Level shifters are integral components of any circuit that operates from different power supply boundaries. Level shifters act as interfaces between different power supply domains to send and receive signals across these boundaries. Depending in part on the voltage mismatch between two power domains, circuit design that reduces duty cycle errors, or duty cycle distortion, becomes increasingly important.
As one skilled in the art will understand, duty cycle is the ratio of the average power to the peak pulse power of a signal, or the ratio of the pulse width to the pulse repetition interval. That is, duty cycle represents the ratio of “on” or logic high pulses to the total operating time or designated signal interval, including “off” or logic low pulses. Thus, duty cycle distortion is a deviation in duty cycle from the intended duty cycle, in particular a variation in the transition from logic high to logic low and/or logic low to logic high. In digital systems, duty cycle distortion is the difference between the duty cycle between a 1 bit and a 0 bit.
The importance of circuit design that accounts for duty cycle distortion significantly increases as the difference between the power supply voltages between two power supply domains gets larger. Additionally, reducing duty cycle distortion has become an even more important issue as chip operating frequencies enter multiple giga-hertz ranges. This design consideration is even more pronounced in analog circuits, which are strongly influenced by process, voltage, and temperature (“PVT”) variations.
Therefore, there is a need for a level shifter system and/or method that minimizes duty cycle distortion due to voltage differences across power domains that addresses at least some of the problems and disadvantages associated with conventional systems and methods.